When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, several strategies have been employed to improve device performance, such as using high-k (HK) dielectric material and metal gate (MG) electrode structures, strain engineering, 3-D gate transistors and ultra-thin body (UTB) semiconductor-on-insulator (SOI) structures. For example, by implementing a strained substrate technology, a better device performance is often achieved by modulating strain in a transistor channel, which enhances mobility (e.g., electron or hole mobility) and thereby conductivity through the channel. As an example of strain technology, an epitaxial silicon germanium (SiGe), or silicon phosphorus (SiP) layer, is formed in source and drain regions in p-type FET (PFET) devices, or n-type FET (NFET) devices, respectively.
As device scale decreases and device density increases, consistency of neighboring structures may be affected. Accordingly, although existing approaches have been generally adequate for their intended purpose, they have not been entirely satisfactory in all respects. For example, when a shallow trench isolation (STI) is formed prior to the formation of a nearby SiGe epitaxy structure, the resulting SiGe epitaxy structure may be quite different from another SiGe epitaxy structure further away from the STI.